1. Field
This invention relates generally to delay compensation circuits, and more specifically a delay compensation circuit that can be used with a driver stage of a switched-mode power supply.
2. Related Art
A switched-mode power supply (hereinafter “SMPS”) is a type of direct current voltage to direct current voltage converter that includes two power transistors in a push-pull configuration and an inductor coupled between the two power transistors and an output terminal of the SMPS.
A driver stage of a SMPS alternately switches the two power transistors on and off. To ensure that only one of the two power transistors are on at any moment, the driver stage creates a dead time that occurs during switching transitions. Dead time is defined as an interval during which both power transistors are off. The dead time occurs at each cycle during a period between when one power transistor turns off and the other power transistor turns on. The presence of the dead time avoids a situation where both power transistors are on simultaneously, which would cause a short circuit current and may also lead to failure of the power transistors. The dead time causes an output voltage of the SMPS to be clamped around −0.6V (one diode voltage drop) due to the effect of the inductor. The dead time inserts losses into the SMPS, and such losses become more significant when the output voltage of the SMPS is relatively low. For example, if a SMPS has an output voltage above 4V, the diode voltage drop during the dead time may not be a problem, but if a SMPS has an output voltage of 1.8V or less, the diode voltage drop during the dead time may compromise efficiency of the SMPS. A SMPS having an output voltage of 1.8V or less is used as a power supply for some microprocessors.
A high switching frequency of a SMPS allows components, such as inductors and capacitors, to be small in size and allows the SMPS to have a fast reaction time relative to changes in load current. Disadvantageously, the losses due to the dead time become more significant as the switching frequency is increased.
FIG. 1 illustrates a known device 100 comprising an output stage of a SMPS 102 coupled to a known driver stage 104. The known driver stage 104 comprises known switcher logic 106, an upper buffer 108, a lower buffer 110, a first comparator 121 and a second comparator 122. The first comparator 121 outputs, to the known switcher logic 106, an F_LATCHA signal. The second comparator 122 outputs, to the known switcher 106, an R_LATCHA signal. The SMPS 102 comprises an upper power transistor 131, a lower power transistor 132, an inductor 134 coupled between the power transistors, and an output terminal 140 of the SMPS, as illustrated in FIG. 1. The SMPS 102 also comprises diodes 135 and 136 that are inherently within power transistors 131 and 132, respectively. A load capacitor 137 and a load resistor 138 are coupled to the output terminal 140 of the SMPS 102.
A variable voltage SWA appears at a node 133 between the two power transistors 131 and 132. The inductor 134 is coupled between node 133 and the output terminal 140 of the SMPS 102. The inductor 134 affects the voltage at node 133. The first comparator 121 compares the SWA voltage with a fixed DC reference voltage VREF, which is typically chosen to be slightly above 0V. The second comparator 122 compares the SWA voltage with a fixed DC reference voltage VREFR, which is typically chosen to be slightly below 0V.
The known switcher logic 106 of the driver stage 104 generates W_VGUA and W_VGLA signals that are fed into the upper buffer 108 and the lower buffer 110, respectively, of the SMPS 102. The known switcher logic 106 generates the W_VGUA and W_VGLA signals based, in part, upon timing of the F_LATCHA signal from the first comparator 121 and the R_LATCHA signal from the second comparator 122.
The upper buffer 108 and the lower buffer 110 output VGUA and VGLA signals, respectively, that alternately turn on and off the two power transistors 131 and 132 such that only one power transistor is on at any moment. The VGUA signal alternately turns on and off the upper power transistor 131. The VGLA signal alternately turns on and off the lower power transistor 132.
Disadvantageously, the known driver stage 104 may be unable to reduce the dead time sufficiently enough for optimal efficiency.
Known driver stages, such as known driver stage 104, may increase the dead time when inherent delays associated with comparators and logic paths have a longer duration than the time of one sweep of the SWA voltage.
Furthermore, inherent delays associated with comparators and logic paths may vary with process, noise, temperature, VDD variation, clock and timing variation, part-to-part variation, and other random effects. The dead time of known driver stages, including known driver stage 104, may increase when such inherent delays are unknown and/or vary.